Cold plates carry heat off the accelerators that train sovereign models and clear sovereign settlement. When the silicon under the ledger runs hot, we move the joules at the die, not the room.
Direct-to-chip cooling puts a liquid-carrying cold plate in contact with the package, capturing the majority of a high-TDP part's heat before it reaches air.
A machined microchannel or skived-fin cold plate mounts directly to the accelerator's integrated heat spreader under controlled bolt torque and a thin thermal-interface layer. Coolant passes millimeters from the die, so the thermal path is metal and liquid rather than metal, air, and a fan wall.
Cold plates absorb the sustained power of dense GPU and custom-accelerator packages that push past what forced air can hold at rack density. Junction temperature stays inside the vendor envelope even under long training runs and continuous inference for sovereign models.
The cold plate captures heat from the main compute die; voltage regulators, memory, and NICs are handled by residual air or secondary plates. We size the split explicitly per board so no serviceable component runs outside its rating.
Quick-disconnect couplings let a node be pulled without draining the loop, and dry-break fittings prevent spillage onto adjacent hardware. A failed sled is swapped without taking the rack offline, which matters when the rack is settling transactions.
The technology cooling loop is engineered as a sealed, monitored circuit with defined chemistry, pressure, and redundancy.
A sealed technology cooling system (TCS) circulates treated coolant through the cold plates and rejects heat across a liquid-to-liquid heat exchanger into the facility water loop. The compute-side fluid never mixes with facility water, isolating the silicon from site-water contaminants.
Coolant is a treated water-glycol or engineered dielectric-adjacent mix with corrosion inhibitors and biocide, matched to the wetted metals in the loop. Chemistry, conductivity, and pH are monitored so galvanic corrosion and biological fouling do not silently degrade the cold plates.
A CDU provides the pumps, heat exchanger, filtration, and flow control for a rack or row, with dual pumps so a single pump failure does not stop flow. It regulates supply temperature above the local dew point to guarantee no condensation forms on cold surfaces inside the rack.
Flow rate, supply and return temperature, and differential pressure are telemetered per rack, and pumps are configured N+1. Loss of flow triggers accelerator throttling before junction limits are reached, protecting hardware that holds sovereign workloads.
Every wetted interface is treated as a potential leak, and the system is designed so a leak is caught, contained, and survivable.
Leak-detection rope runs along drip paths and manifolds, and point sensors sit at low points and under couplings. A detected leak raises an alarm with rack and row location so response is directed, not a floor-wide hunt.
Quick disconnects seal on both halves when parted, so servicing a node does not release coolant. The volume that can escape from any single break is bounded by design, not left to chance.
Manifolds and CDUs sit over drip containment that routes any escape away from power distribution and into a captured path. Coolant selection favors low electrical conductivity so an incidental leak is less likely to fault live busbars.
On a confirmed leak the affected loop segment can be isolated and its accelerators throttled or shut down in a controlled sequence. The failure mode is a cooled, powered-down node rather than a thermal runaway on hardware running the sovereign stack.
The same principles that govern the keys and the ledger govern the plumbing that keeps the silicon alive.
Cold plates, CDUs, coolant, and spares are specified so the loop can be maintained by in-nation staff without a foreign service dependency in the critical path. The nation that owns the compute owns the ability to keep it running.
Direct-to-chip lets an owner pack sovereign training and inference into fewer racks and a smaller secured footprint. A tighter physical envelope is easier to place inside a controlled facility and a defined data-residency boundary.
Flow, temperature, and pressure telemetry feed the same monitored operations posture as the compute itself, so thermal health is an auditable part of running the platform. Cooling events are recorded, not lost to a separate building-management silo.
Cooling capacity is sized to the accelerators the owner actually deploys for CBDC, tokenization, and model training, with headroom for the next generation of hotter parts. The thermal design is part of the platform engineering, delivered under EPC alongside the compute.